[LAD] [Jack-Devel] jack2's dbus name

[Jussi Laako]

Florian Schirmer wrote:
> I think this is incorrect. The total latency should be inputhw 
> +2*blocksize+outputhw.

Ahh, yes, sure. I seem to be a bit tired today...

And most of the time there's just one interrupt which can be thought as 
"buffer switch" interrupt. Unless there are two different cards running 
out of same word clock (slightly problematic case anyway).

Thus even more important to keep blocksize as small as possible...


	- Jussi