[LAD] A little quiz about audio measurements...

Ralf Mardorf ralf.mardorf at alice-dsl.net
Fri May 28 18:03:05 UTC 2010


Olivier Guilyardi wrote:
> On 05/28/2010 07:36 PM, Ralf Mardorf wrote:
>   
>> Folderol wrote:
>>     
>>> On Fri, 28 May 2010 19:20:54 +0200
>>> Ralf Mardorf <ralf.mardorf at alice-dsl.net> wrote:
>>>
>>>  
>>>       
>>>> Veronica Merryfield wrote:
>>>>    
>>>>         
>>>>> You can't trust a loop back test.
>>>>> Any instability or dither on the reference clock of card A (fifo
>>>>> clocking say) is not going to show in a loop back test.
>>>>> Vrnc
>>>>>       
>>>>>           
>>>> Is Veronica Merryfield the winner?
>>>>     
>>>>         
>>> I'm highly suspicious of the USB link, but can't quite put my finger
>>> on why.
>>>   
>>>       
>> Card A is the USB card. For USB there could be several issues, but I
>> don't have knowledge about buffering etc., but I guess it's card A and
>> that there's  a "instability" = jitter. I don't know what dither for CLK
>> is. I guess the winner is Veronica Merryfield.
>>     
>
> I mentioned the clock problem first ;-) However, I thought it the other way
> around: I said that clocks being asynchronous that would generate artefacts, but
> Veronica seems to say that these are hidden when using a single clock.
>
> That's pretty much the same thing to me :p
>
> --
>   Olivier
>   

Did you also say for what card? A or X? If so, is Oliver the winner?

Btw.:

Ralf Mardorf wrote:
> Gabriel Beddingfield wrote:
>> On Fri, May 28, 2010 at 12:39 PM, Gabriel M. Beddingfield
>> <gabrbedd at gmail.com> wrote:
>>  
>>> The 100 Hz (being 2x 50Hz, the power freq. in Italy)
>>> suggests that it is probably related to some manner of
>>> power supply.  However, I have no theory why we're
>>> getting 2x 50Hz (and I think I need one :-)).
>>>     
>>
>> Doh!  When the AC wave is rectified, it results in a signal that is 2x
>> the freq. because the negative part gets inverted.  That's why we see
>> 100 Hz instead of 50 Hz.
>>
>> -gabriel
>>   
>
> On card A or X?
> Why AM and not additive signals? 

Is the jitter caused because of residual ripple?

Summarized:

Residual ripple for the DC could cause clock jitter and this for card A.



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