[LAD] media clock from wall clock

[Fons Adriaensen]

On Sun, Oct 12, 2014 at 08:50:31AM -0700, Len Ovens wrote:

> The first thing I find is that it is not possible to get even word
> clock via simple math. The wall clock moves one tick per usec which
> at 48K is 20.833rep. (44.1k is a mess) I would suggest this is why
> AVB and AES67 at lowest latency already uses 6 sample frames which
> is a nice even 125 usec.

This is a non-problem. A PLL/DLL (which is what any system that 
syncs one clock to another will amount to) can be made for any
ratio of integers. 

The real problem here (but it's not a new one, solutions for
this have been known for a long time) is a different one.
If the media clock is to be used for actual AD/DA conversion 
(and oterwise you don't need it) it needs to have very low
jitter aka phase noise. 

When you multiply a frequency by a factor of N then within
the BW of the control loop the phase noise density will be
multiplied by N^2. So you need a PLL/DLL with a very low BW.
Which normally means that the capture range will be very
small as well, and the loop may never lock for typical 
initial conditions. As said there are solutions for this,
but you need to design for it.
 
Ciao,

-- 
FA

A world of exhaustive, reliable metadata would be an utopia.
It's also a pipe-dream, founded on self-delusion, nerd hubris
and hysterically inflated market opportunities. (Cory Doctorow)