[LAD] Jitter analysis

benravin ben.alex at outlook.com
Fri Oct 6 18:03:01 UTC 2017

Fons Adriaensen-3 wrote

> It's impossible to say anything about this if you don't provide
> numbers. How big is the resulting resampling ratio variation ?
> If a few ms jitter leads to anything perceptible then your DLL
> and/or resampling control loop are not dimensioned correctly,
> or there is another basic problem with your design.

Actually I'm working on Embedded Linux. I have a requirement to configure
the SoC as audio output master or slave. If I use the SoC audio output as
slave and DAC as master then zita-ajbridge will work as expected. 

But if SoC audio output is configured as master and DAC as slave and use the
SoC system clock for timestamping the write and read buffers, then any drift
on SoC clock will not be detected. 

For example:

At the write side, t_wA and t_wB are the timestamps of buffer1 and buffer2
 and read side t_rA and t_rB

t_w = t_wB - t_wA
t_r = t_rB - t_rA 

error = (t_r – t_w ),  

This error is minimized by audio control loop. 

And if SoC is configured as master then any drift on write side will be
there on read side as well. How to detect and correct it ?


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