[LAU] Dual Delta Setup

Len Ovens len at ovenwerks.net
Thu Jan 3 03:15:05 UTC 2013

On Wed, January 2, 2013 4:05 pm, Fons Adriaensen wrote:
> On Wed, Jan 02, 2013 at 03:35:17PM -0800, Len Ovens wrote:
>> After some thought, I am thinking this may be the issue, at least with
>> delta series IFs. They use phase locked loops for both word clock and
>> S/pdif. From some of the comments I have heard/read these are medium
>> quality devices and "in sync" may mean some wandering on the slave
>> device
>> (voltage regulation is poor and heats the card for example). This could
>> mean that the interrupt timing on the slave could move from preceding
>> the
>> master to lagging at the phase lock hunt rate.
> Rather improbable. If the PLL on the SPDIF wouldn't work OK, you
> wouldn't be able to input SPDIF in the first place. It takes more
> than sample accuracy to clock and read the bits correctly.

Right, That should have been obvious. Bit rate is much higher than sample
> Imagine that the counter and logic that define a period already start
> running on the card when ALSA sets the HW parameters (i.e. before the
> start command). And then, instead of resetting that logic and starting
> a period exactly when the start command is given, the card simply enables
> the interrupt to the PC. There will be a random delay between the start
> command and the actual start of the first period.
> For a single card things would just work. But it would be impossible
> to sync two of them properly.

I would think in that case no two of them would work...Well maybe.
Assuming that the cabling is done with power off, they should be pretty
close on power up... though it is probably easy to poke holes in that too.

The device is designed to sync with a second one, I wonder how they make
it work in windows.

Len Ovens

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