One approach that I’ve used with good success here is to run the decoded PCM through a FIFO buffer between the SRC and the play-out stages and then use the size of that FIFO (which will change dynamically in response to things like network congestion) to feed a PLL that drives the converter ratio for the SRC stage. The trade-off for this approach of course is increased latency. If true low-latency operation is required, then some sort of clocking (ala AES67) will be required.
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| Frederick F. Gleason, Jr. | Chief Developer |
| | Paravel Systems |
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| A room without books is like a body without a soul. |
| -- Cicero |
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