[LAD] How is the TSC calibration accuracy on dual core 2 computers? (And what about HPET?)
Kjetil S. Matheussen
k.s.matheussen at notam02.no
Tue Apr 28 17:43:09 UTC 2009
On Tue, 28 Apr 2009, Steve Harris wrote:
> I don't know about jitter, but certainly a few years ago, you sometimes got
> stalls - eg. under heavy DMA load. That may not be an issue with modern CPUs
> and chipsets. I think I posted some code that demonstrated it to the l-a-d
> list at the time, but good luck finding it :)
Thanks for the warning. I'm not planning to run other programs or do any I/O
besides audio though. And to avoid rescheduling while my code
snippets run, I'll probably set the threads to SCHED_FIFO/99 too.
Hopefully that'll give accurate results.
Paul Davis wrote:
> the cycle counter on intel systems is (was?) guaranteed to run exactly
> in sync. AMD had a problem a few generations back where they neglected
> to provide this feature and it caused havoc for several different
> categories of users. they corrected their error very quickly and i
> believe that all their chipsets will now also always have precisely
> A synced cycle counter.
> in the absence of frequency scaling, there is no jitter that can be
> measured using anything else you're likely to have attached to the
Sorry, really bad use of the word "jitter" on my part. I ment
slightly wrong values caused by unsynchronized tsc clocks.
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