17 Dec
2009
17 Dec
'09
9:56 a.m.
On 12/17/2009 01:03 PM, Tim Blechmann wrote:
There also are bugs on ARM, x86-64, etc..
+#if
defined(__APPLE__)
+#include <libkern/OSAtomic.h>
+#define MEMORY_BARRIER() OSMemoryBarrier()
+#elif (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1)
+#define MEMORY_BARRIER() __sync_synchronize()
+#else
+#warning SMP Danger: memory barriers are not supported on this system
+#endif
there was a buggy gcc version, that didn't implement
__sync_synchronize() correctly on x86, causing errors on nehalem
machines (which don't have a shared cache). if sse is enabled, _mm_mfence() can be used to work
around this compiler
bug ...
IMO, it's the compiler job to figure how to implement a memory barrier.
Otherwise, we're going to end up with a 200 lines macro def, with a workaround
for this, a workaround for that,... GCC devs are more competent for this I
think, and will keep it up-to-date.
--
Olivier