26 Nov
2009
26 Nov
'09
5:03 a.m.
On Thu, 26 Nov 2009 03:44:51 +0100
Jens M Andreasen <jens.andreasen(a)comhem.se> wrote:
On Thu, 2009-11-26 at 01:24 +0000, Folderol wrote:
ADCs with built-in very fast conversions (1-2uS), externally triggered
by precision tunable oscillators, these (across different boards)
frequency locked by very slow, averaging FLLs. Phase may be skewed but
frequency should be held.
It's late, but I can't sleep, so...
set sample rate -> 44.1, 48, 96, ?
(default 48)
If anyone can see any obvious holes in this or
simplifications please
say so.
Crystals controlling inexpensive DAC'c and ADC's will be drifting. There
should be a solder-iron solution for that, but only as long as they live
in the same box. Upsampling to 192k at the receiving end to better hide
the
skipped/inserted samples might be an idea.
Or possibly interpolation between the two either side of the missing
one.
--
Will J Godfrey
http://www.musically.me.uk
Say you have a poem and I have a tune.
Exchange them and we can both have a poem, a tune, and a song.