19 Apr
2005
19 Apr
'05
9:10 a.m.
Paul, from what I understand about the Spartan/FPGA on
the HDSP board
almost anything the card can do is configurable. Is that not valid for
the specific register you mention?
the FPGA is running firmware burnt into an EPROM on the board. the
stuff that the driver downloads does not control the FPGA, it controls
the i/o operation of the breakout box. the firmware on the EPROM only
knows about a few distinct interrupt-generating intervals. you'd have
to rewrite and reflash the EPROM to get a different interval, but RME
has never provided access to this firmware.
buffersize. Ok. Could it be that the reason to do this
is to play it
safe, in order to have rock solid operation on just about every
platform? That this is not constrained technically?
i am sure the FPGA could be programmed to send interrupts every frame
if you wanted. the lower practical limit is the PCI burst size, which
i think is about 16 frames. i suspect that the lower limit of 64 was
influenced by the performance of windows and mac systems when RME
first started the hammerfall line.
--p