12 Nov
2002
12 Nov
'02
12:30 p.m.
> Can gcc 3.2 target archtitectures higher than the
PII ?
> (I mean generating P3/P4 specific code ?)
Yes, you have to specify the use of sse explicity (I
think I meantioned it
on IRC when we were benchmarking). It appeared to make zero difference on
the athlon, but I didn't check the assemler to see exactly what it was
doing. I've heard that just using sse instructions instead of 387 on the
P4 is quicker, but I've not tried it. Gcc will do that if you specify -msse
The sse instructions ought to be substantially faster. There are many more
registers available to support the flops, and they aren't organized into the
ridiculous 387 stack, so they're easier to reach. I believe they also
default
to round-to-nearest and flush-denormals, but if you care about such niceties
you should check.
-BobC