6 Apr
2006
6 Apr
'06
6:14 p.m.
On Wed, Apr 05, 2006 at 07:52:26PM -0500, Richard Smith wrote:
Getting that to fly in an FPGA however may be the
problem as you start
running into clock speed limits. And an ASIC suffers from the lack of
startup cash.
I've seen a 64 channel interface fit into a single Spartan 2E that was
small enough to be supported free Xilinx Webpack. Since then, the
current web pack supports spartan3s that are bigger and faster than that
project used.
--
Joshua D. Boyd
jdboyd(a)jdboyd.net
http://www.jdboyd.net/
http://www.joshuaboyd.org/