9 Dec
2003
9 Dec
'03
8:03 a.m.
Hi,
tisdagen den 09 december 2003 12.22 skrev Steve Harris:
On Tue, Dec 09, 2003 at 09:25:42AM +0100, Clemens
Ladisch wrote:
USB isochronous transfers happen once per millisecond.
OK, so its the difference between 44 or 45 samples per packet at 44.1kHz
(USB) and 5 or 6 (1394).
So, a plausible jack period of 64 samples will be 11 or 12 1395 packets,
but always 125uS of jitter of course, (10 or 11 packets at 48k).
I dont really have any idea how bad that is, its 8% of the availble time
slot for processing the 64 samples.
You could lessen the effect of the jitter by having triple-buffering in
software, as in a 3x64 PCI soundcard - I dont know wether thats better
than just going to 128 samples or not.
FWIW, for my needs I rarely go below 256 samples/period anyway, even
though my setup is capable of it, but I understand there are people who
really need very low latency.
At 256 samples/period the jitter is only 2.1% of the time slice, which is
unlilkly to matter - cache temperature and so on has a far greater effect
than that.
Though it is interesting debating the technical merits of firewire, for me,
atleast, it would be far more interesting to get it actually working. I'm
_very_ interested in utilizing these hardwares.
I googled a little last night, some people we all know popped up here and
there (Hi Steve, Mark and Bob).
There was a LAD message from 2001, someone who had been in contact with Yamaha
and it seemed they(Yamaha) where working towards making mLan a part of the
A&M standard (I think I got that right...not sure)... now... I'm not entirely
sure what this means. It seemed as the A&M standards also cost a lot of
money?
Do we have enough information to implement mLan support?
As I understand it, Bob Ham had/is working on implementing 61883 support for
Jack, which seems like it's needed for mLan, a layer below it perhaps? How
far has this come, is there something one can test somehow, what hardware do
one need?
Regards,
Robert
ps.
I'm cc:ing LAD as I'd like to move the discussion there. Remove LAU if you
respond to this.
ds.
I seem to recall that it does, but that the packet
size is smaller,
making the latency problem easier to deal with.
Isoch - 1394 has a timer operating on the bus. This timer happens
(roughly) every 125uS.