15 Apr
2005
15 Apr
'05
4:46 a.m.
Paul, Thomas,
What are the constraints for the HDSP 9652's apparent minimum buffer
size of 64 frames? Is it the FPGA? Is it the firmware?
Wolfgang
15 Apr
15 Apr
9:09 a.m.
What are the constraints for the HDSP 9652's
apparent minimum buffer
size of 64 frames? Is it the FPGA? Is it the firmware?
whatever stuff is programmed into the FPGA and/or the rest of the
board, it cannot be set to generate interrupts at smaller intervals
than this.
2:19 p.m.
Paul Davis <paul(a)linuxaudiosystems.com>om>:
Paul, would you think it's worth trying to find out deeper detail on
this? Me thinking if the 9652 can do 96khz/64 frames (1.33 msecs) it
can actually go quicker than the 44.1khz/64 frames (2.9 msecs) setup.
Is there any potential or would one only waste time?
Wolfgang
What are the
constraints for the HDSP 9652's apparent minimum buffer
size of 64 frames? Is it the FPGA? Is it the firmware?
whatever stuff is programmed into the FPGA and/or the rest of the
board, it cannot be set to generate interrupts at smaller intervals
than this. 
2:38 p.m.
On Fri, 2005-04-15 at 18:18 +0200, Wolfgang Woehl wrote:
Paul Davis <paul(a)linuxaudiosystems.com>om>:
Paul, would you think it's worth trying to find out deeper detail on
this? Me thinking if the 9652 can do 96khz/64 frames (1.33 msecs) it
can actually go quicker than the 44.1khz/64 frames (2.9 msecs) setup.
Is there any potential or would one only waste time?
Well, what happens if you just change the driver to allow 44.1/32? It's
probably one or two lines of code.
Lee
What are
the constraints for the HDSP 9652's apparent minimum buffer
size of 64 frames? Is it the FPGA? Is it the firmware?
whatever stuff is programmed into the FPGA and/or the rest of the
board, it cannot be set to generate interrupts at smaller intervals
than this.
3:15 p.m.
On Fri, 2005-04-15 at 18:18 +0200, Wolfgang Woehl
wrote:
you guys are not understanding me. when you set the buffer size, you
are setting a register value in the HDSP. the h/w doesn't understand
any values lower than 64. in fact, it not only doesn't understand, it
has no way to even request it.
--p
Paul Davis <paul(a)linuxaudiosystems.com>om>:
Paul, would you think it's worth trying to find out deeper detail on
this? Me thinking if the 9652 can do 96khz/64 frames (1.33 msecs) it
can actually go quicker than the 44.1khz/64 frames (2.9 msecs) setup.
Is there any potential or would one only waste time?
Well, what happens if you just change the driver to allow 44.1/32? It's
probably one or two lines of code. What are
the constraints for the HDSP 9652's apparent minimum buffer
size of 64 frames? Is it the FPGA? Is it the firmware?
whatever stuff is programmed into the FPGA and/or the rest of the
board, it cannot be set to generate interrupts at smaller intervals
than this.
3:28 p.m.
On Fri, 2005-04-15 at 13:18 -0400, Paul Davis wrote:
you guys are not understanding me. when you set the
buffer size, you
are setting a register value in the HDSP. the h/w doesn't understand
any values lower than 64. in fact, it not only doesn't understand, it
has no way to even request it.
Oh, ok. Should have looked at the code.
Lee
19 Apr
19 Apr
8:37 a.m.
Paul Davis <paul(a)linuxaudiosystems.com>om>:
Paul, from what I understand about the Spartan/FPGA on the HDSP board
almost anything the card can do is configurable. Is that not valid for
the specific register you mention?
It's obvious that RME sells the cards with a lower boundary of 64 frames
buffersize. Ok. Could it be that the reason to do this is to play it
safe, in order to have rock solid operation on just about every
platform? That this is not constrained technically?
Thanks in advance for any further information.
Wolfgang
On Fri,
2005-04-15 at 18:18 +0200, Wolfgang Woehl wrote:
you guys are not understanding me. when you set the buffer size, you
are setting a register value in the HDSP. the h/w doesn't understand
any values lower than 64. in fact, it not only doesn't understand, it
has no way to even request it. Paul Davis <paul(a)linuxaudiosystems.com>om>:
Well, what happens if you just change the driver to allow 44.1/32?
It's probably one or two lines of code. >What are the constraints for the HDSP
9652's apparent minimum
> buffer size of 64 frames? Is it the FPGA? Is it the firmware?
whatever stuff is programmed into the FPGA and/or the rest of
the board, it cannot be set to generate interrupts at smaller
intervals than this.
Paul, would you think it's worth trying to find out deeper detail
on this? Me thinking if the 9652 can do 96khz/64 frames (1.33
msecs) it can actually go quicker than the 44.1khz/64 frames (2.9
msecs) setup. Is there any potential or would one only waste time?
9:10 a.m.
Paul, from what I understand about the Spartan/FPGA on
the HDSP board
almost anything the card can do is configurable. Is that not valid for
the specific register you mention?
the FPGA is running firmware burnt into an EPROM on the board. the
stuff that the driver downloads does not control the FPGA, it controls
the i/o operation of the breakout box. the firmware on the EPROM only
knows about a few distinct interrupt-generating intervals. you'd have
to rewrite and reflash the EPROM to get a different interval, but RME
has never provided access to this firmware.
buffersize. Ok. Could it be that the reason to do this
is to play it
safe, in order to have rock solid operation on just about every
platform? That this is not constrained technically?
i am sure the FPGA could be programmed to send interrupts every frame
if you wanted. the lower practical limit is the PCI burst size, which
i think is about 16 frames. i suspect that the lower limit of 64 was
influenced by the performance of windows and mac systems when RME
first started the hammerfall line.
--p
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7 comments
3 participants
participants (3)
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Lee Revell -
Paul Davis -
Wolfgang Woehl