13 Nov
2009
13 Nov
'09
3:56 p.m.
On Fri, 13 Nov 2009 14:57:51 +0100 (CET)
karl(a)aspodata.se (Karl Hammar) wrote:
Folderol:
I think it actually only needs to be less that 10uS
karl(a)aspodata.se (Karl Hammar) wrote:
...
An entire cycle of 48kHz is about 20 uS so jitter
would have to be
significantly less than that to avoid 'cogging'.
So jitter < 1us would be required ? What is "cogging" ?
The effect you can get with a system with poor stability but very strong
locking when incoming pulses are half way between the wanted times
(used to happen a lot with early discrete PLLs). The system will
alternately lock on the early and late pulses. The correction waveform
looks like a cog railway :)
--
Will J Godfrey
http://www.musically.me.uk
Say you have a poem and I have a tune.
Exchange them and we can both have a poem, a tune, and a song.