15 Nov
2009
15 Nov
'09
5:53 p.m.
Folderol:
There is a chip select
feature,
The chip select comes with the spi bus interface, which(s) chip shall
respond to the clock.
Do we understand each other correctly?
With a parallell bus I mean a bus with multiple data lines and multiple
address lines. Examples of parallell buses are ISA and PCI.
For the above chip you connect 16data lines cpu<->chip, the address
lines from the cpu must be connected to some decoding logic defining
the chips address.
To use this chip you activates sync, wait till all chip signalled drdy
and for each chip do two read cycles. The ad7762 has a 16bit wide data
bus, and one could potentially put one chip on the top half and another
on the lower half of the processors 32wide data bus. I don't know the
memory interface speed of the sam9260, but if it is 10MHz and you spend
two read cycles to get the data for two chips, the raw data rate would
be 10Mwords / s. If you divide that with 96kHz, you see that the bus
limit is 100channels (with a few ifs). Where the bus limit on spi
would be more along the lines of 8-16 channels.
karl(a)aspodata.se (Karl Hammar) wrote:
> Folderol:
...
For rough testing it could be used to lock a pair of
ADCs. TLC4545ID
looks like a good (cheap) possibility here.
Found it, datasheet at [1], it seems
to cost ~12USD. There is no
"start" pin to be able to simultaneously start multiple converters.
And you cannot daisychain this chip. [2] can be daisy-chained, but
with a maximum of eigth channels, but it can be synced. and also a count overrun, both of which
put the output into high Z state. Therefore the outputs can be
paralleled, and count pulses sent to the appropriate chips by the
processor.
That is normal for chips with spi bus.
It also has an interesting feature of having it's
own high
speed conversion clock,
Some has an internal clock and some need an external. At most this will
affect component count.
so presumably, once a conversion has been
done you can read the result at your leisure - not sure how this would
actually work. I hadn't read far enough to find out if/how this could
be synced.
It doesn't seem to be an easy way to sync TLC4545ID's. The sampling
start after 5 clcks after chip_select, it need another 20 clcks for the
sampling. Then you release the chip and it will convert the analog value
to digital and it takes < 2.94us. During the sampling time the previous
is clocked out.
That is why I'm looking for a "start" pin on the chip, to be able to
say to all ADCs to start simultaneously.
If we are
going to have multiple analog inputs at higt sample rate,
isn't it better to have a parallell interface. With spi the number of
channels will be limited to something like 8 for a 24bit converter.
Plus that the AT32AP7000/AT91SAM9260 only has two spi-busses.
Maybe ad7762 [2] could be useful (28 USD),
Not sure how you'd effectively squeeze in multiple channels of 24 bits
parallel without quite a lot of juggling. Also don't know how fast the
spi interface can run.
According to [4] you can run it up to 50MHz, but it depends on the
cpu and the chip you are communicating to, so 5-10MHz is more of what you
can expect.
...
> [1]
http://focus.ti.com/lit/ds/symlink/tlc4545.pdf
> [2] http://www.analog.com/static/imported-files/data_sheets/AD7764.pdf
> [3] http://www.analog.com/static/imported-files/data_sheets/AD7762.pdf
Regards,
/Karl
[4] http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
-----------------------------------------------------------------------
Karl Hammar Aspö Data karl(a)aspodata.se
Lilla Aspö 148 Networks
S-742 94 Östhammar +46 173 140 57 Computers
Sweden +46 70 511 97 84 Consulting
-----------------------------------------------------------------------