17 Feb
2009
17 Feb
'09
3:13 a.m.
Hi,
On Monday 16 February 2009 22:14:41 Fons Adriaensen wrote:
I am glad I buy the finished product where the signal goes in and digital
memory blocks come out via pci!
But not only do they sync up to four AD-converters to get one channel with
4GS/s (current state of the art is 8GS/s!), they also sync several of these
devices to act as one digital oscilloscope with multiple channels. They do the
syncing by 10MHz clock and somehow manage to distribute the trigger event to
all devices involved. Quite spooky and lot of hf to deal with.
Anyway, I wish I knew as much as you, Fons, about DSP. Current results (which
I am presenting tomorrow) aren't really encouraging...
Have fun,
Arnold
On Mon, Feb 16, 2009 at 09:27:18PM +0100, Arnold
Krille wrote:
Thanks for that! I guess the one who told me my information (a phd here at
university) had only knowledge from the earlier days of digital sound.
Are they really upsampling?
I was under the impression that they use one fast converter (far faster
then the sampling rate you hear) and the (de-)multiplex the signal to the
various channels. Should be easier than syncing several converter clocks.
AFAIK
nobody is doing that today. Some of the very early
Sony converters for recording digital audio on video tape
used to do this, compensating for the half sample delay
on the second channel by the same trick on playback.
Just consider this: a very good digital antialiasing
filter operating at 8 * Fs (i.e. 8 * upsampling) costs
almost nothing if integrated on the DA chip. An analog
one for 44.1 or 48 kHz would require precision components,
very careful board design, and probably manual alignment
of each individual board. The choice is easy to make... The devices I
work with on the other hand go exactly
the other way, they combine several 1GS/s adc's to
have one 4GS/s adc. But they face their own set of
clock-sync problems...
I imagine they have !! The fastest one I was involved
with was 1G, it drove most of the design team crazy,
and required a collection of dirty tricks to get it
interfaced to an FPGA, but that was five years ago...